An inverter operates in response to an input signal to provide an output signal that is the inverse of the input signal. With the development of electronic technology, inverters are widely employed. For example, an inverter may be employed in a transmission driving circuit of an organic light-emitting display device to provide a corresponding electric potential for a pixel compensation circuit electrically connected with the transmission driving circuit, so that the pixel compensation circuit can accomplish node initialization, threshold value compensation, data writing and the like.
FIG. 1A is a circuit diagram of an inverter in the related art. As shown in FIG. 1A, the inverter includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4 and a capacitor C0, where the first to fourth transistors P1 to P4 are all P-Channel Metal Oxide Semiconductor (PMOS) transistors. A gate electrode of the first transistor P1 is electrically connected with an initial signal input terminal IN0 for receiving an initial signal, a source electrode of the first transistor P1 is electrically connected with a first electrical level signal input terminal VG1 for receiving a first electrical level signal, and a drain electrode of the first transistor P1 is electrically connected, via the capacitor C0, with a first clock signal input terminal CK1 for receiving a first clock signal; a gate electrode of the second transistor P2 is electrically connected with a second clock signal input terminal CK2 for receiving a second clock signal, a source electrode of the second transistor P2 is electrically connected with both the drain electrode of the first transistor P1 and a gate electrode of the fourth transistor P4, and a drain electrode of the second transistor P2 is electrically connected with a second electrical level signal input terminal VG2 for receiving a second electrical level signal; a gate electrode of the third transistor P3 is electrically connected with the initial signal input terminal IN0, a source electrode of the third transistor P3 is electrically connected with the first electrical level signal input terminal VG1, and a drain electrode of the third transistor P3 is electrically connected with an output terminal OUT0 for outputting an output signal; a source electrode of the fourth transistor P4 is electrically connected with the output terminal OUT0, and a drain electrode of the fourth transistor P4 is electrically connected with the second electrical level signal input terminal VG2. Here, the first electrical level signal is a constant high level signal, and the second electrical level signal is a constant low level signal.
FIG. 1B is a diagram showing waveforms of various signals of the inverter shown in FIG. 1A. As shown in FIG. 1B, SIN0 represents the initial signal, SCK1 represents the first clock signal, SCK2 represents the second clock signal, and SOUT0 represents the output signal. When the first clock signal SCK1 changes from a low level to a high level, an electric potential of the gate electrode of the fourth transistor P4 is affected and hence the turning-on of the fourth transistor P4 is affected because of an Bootstrap effect of the capacitor C0 (i.e. electric charge of the capacitor C0 is conserved), so that transmission of the second electrical level signal to the output terminal OUT via the fourth transistor P4 is affected, and the value of a low level of the output signal SOUT0 is affected, thus resulting in instability of the output signal.